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专利名称：bus access arbitration circuit and bus access

arbitration method

发明人：竹内 俊樹

申请号：JP2014507040

申请日：20121227

公开号：JPWO2013145062A1

公开日：20150803

专利附图：

摘要： transfer throughput is not deteriorated, and, also allows cycle security of

worst-case I it is an object. Bus access arbitration circuit (300) includes access mode

determination unit (100) and the round-robin arbitration unit (200). Access mode

determining unit (100) determines whether if a bus access from a plurality of masters M0,

M1 is generated, the access mode for each master to be connected is the continuous

access mode or single access mode. Round-robin arbitration unit (200), depending on the

access mode, dynamically switches the access arbitration scheme for arbitrating bus

access. Access mode determination section (100), the access interval counting unit (10)

comprises a continuous access number counting unit (20), determines the access mode

status register the status of the access mode stored in each master (40), Based on the

continuous access count and access interval, and updates the state of the access modes.

申请人：日本電気株式会社

地址：東京都港区芝五丁目７番１号

国籍：JP

代理人：家入 健

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