TMAX精简教程

一、TMAX的使用

1. 工具接口

Basic input of TetraMAX to perform ATPG are the vendor gate-level simulation

libraries, design netlist, command script and test procedure file. Main output data are

the test patterns and reports on results. In order to read in netlist and library files, use

the “read netlist” command or the Netlist button of the GUI. The netlist format

(Verilog, EDIF, VHDL) is automatically detected. It is recommended you use Verilog

as the netlist input format. TetraMAX also automatically detects netlist compression

(none, GZIP, proprietary binary). A single file may contain one or more modules. By

using multiple files, mixed language netlists are supported. A single read command

may use wildcards to match multiple files using the „?‟ and „*‟ characters.

Example:

read netlist /proj/mars/lander/shared/*/??DFF*.v

There is no restriction whether to use flat or hierarchical netlists.

Standards for pattern input: VCD-E, WGL, STIL.

Standards for pattern output: Verilog, WGL, STIL, VHDL.

Multiple pattern compression techniques (static & dynamic).

Built-in GZIP compression support for file inputs and outputs (designs, libraries,

protocols, patterns, fault lists).

2. 使用流程

The diagram illustrates the basic test pattern generation flow. The three operation

modes of TetraMAX are shown by different colors. During build mode the design and

libraries are read in, and the ATPG model of the design is built. If the build step was

successful, you automatically get into DRC (design rules checking) mode. Here you

specify all information needed by the tool to configure the design for test. The test

procedure file (STIL = Standard Test Interface Language) is read in. If DRC was

successful, you get into Test mode. You finally adjust settings for ATPG, start pattern

generation, perform pattern compression and save the patterns to disk.

STEP:

(1) Reading the Library Files

Use NETLIST button or read netlist command: BUILD> read netlist mylibrary.v

Read netlists in hierarchy order, from library leaf cells (first) to top level module (last).

Example:BUILD> read netlist /libs/0.18u/*/??DFF*.v

In case of duplication when reading in netlists, the default behavior is to keep the last

module definition encountered. Netlist type (Verilog, EDIF, VHDL) is automatically

detected. Netlist compression (none, GZIP, proprietary binary) is automatically

detected. A single file may have one or more modules. A single read command may

use wildcards to match multiple files using the „?‟ and „*‟ characters.

(2) Read Design Netlist

Use NETLIST button or read netlist command:BUILD> read netlist my_asic.v

Designs may be described using forms of:

Verilog structural netlists;

EDIF structural netlists;

VHDL structural netlists;

Mixtures of the above -- note: beware of naming convention restrictions of each

language;

Netlists may be either flat or hierarchical;

Netlists may exist as a single file or multiple files.

(3) Build the ATPG Design Model

Use NETLIST button or build model command: BUILD> run build_model my_asic

The build process is used to choose the top-level module and to build the in-memory

design image necessary for the ATPG algorithm.

You may also build at any intermediate level. Synopsys recommends that you read in

the library first, then the DUT netlist, otherwise, specify top-level in build command.

(4) Perform Design Rule Checks

Use DRC button or run drc command: DRC> run drc

Scan Testing Rules Checked During DRC:

(S rules) The scan chains are checked for working order during shift mode and that

the scan input to output path is logically connected.

(C rules) Clocks and asynchronous set/reset ports connected to scan flops are

checked to see that they are controlled only by primary inputs.

(C rules) Clocks/sets/resets are checked for off state when switching from normal

mode to scan shift mode and back again.

(Z rules) Multi-driver nets are checked for contention.

run drc in TetraMAX is nearly identical to dft_drc in DFT Compiler:

PI = Primary Input;

PO = Primary Output;

Constraint = a restriction to be honored when generating ATPG patterns;

Gate ID = unique integer assigned to each distinct ATPG primitive in the flattened

design;

CLOCK = any signal that affects the stored state of a sequential device including

asynchronous sets and resets as well as RAM write controls.

(5) Prepare for ATPG

Running ATPG with ATPG button or run atpg command: TEST> run atpg -auto

Always start with –auto. It provides the best starting point and tradeoff between

coverage and pattern count in the current and future releases. Most (though not all) of

these ATPG options are specified by the set atpg command. The Run ATPG dialog

box shown can invoke set atpg, run atpg, and other commands. A key choice on the

dialog is fault model: click the radio button for one of three models, or run command:

TEST>set faults –model stuck. Given the fault model, you can then inject all

possible SAFs by clicking Add all faults, or run command: TEST>add faults -all.

(6) Review Summary Report

Use SUMMARY button or run summary command:

SUMMARY> report summaries faults patterns > /* save_path/file_

Options to Report Summaries.

Primitives: Reports the ATPG primitive summary.

Faults: Reports the fault summary. The display of collapsed versus uncollapsed fault

categories or normal versus verbose fault class detail is controlled by use of the set

faults command.

Patterns: Reports the pattern count.

Library_cells: Reports the library cells. A report includes the name of the library cell

and the number which have been instantiated in the flattened design. NOTE: This

count may differ slightly from an ASIC vendor' s report of the same data due to circuit

optimization done for ATPG purposes which may result in the elimination of certain

internal gates.

Memory_usage: Reports total RAM usage by the process and well as the RAM used

by the data space patterns + design of the process. NOTE: This report is available

only on UNIX platforms.

Optimizations: Reports the gate optimization and removal performed during the run

build process.

Sequential_depths: Reports the maximum Fast-Sequential depth for controlling,

observing, and detection, and a representative gate ID for each.

Cpu_usage: Reports the cumulative CPU usage since starting the tool for selected

operations such as reading netlists, performing model builds, generating ATPG

patterns, compressing patterns, etc.

(7) Saving ATPG Patterns

Use WRITE PATTERNS button or run write patterns command:

WRITE PATTERNS >

write patterns /*save_path/ file_ -replace -internal -format stil –serial

There are many options for pattern output configuration. File Format specifies the

format the patterns should be written with. Note that there are some more variations

of Verilog, e. g. serial or parallel scan load, and VHDL or VHDL93. You can specify

which pattern type to exclude from the pattern output. All types are written by default.

By specifying a pattern range you can select which patterns should be written to the

file. This is useful for simulation and debugging purposes. If you need to generate

multiple smaller pattern files instead of a single one containing all patterns, use the

split option. You can further specify the type of data compression to be used: none,

GZIP, or Binary. Binary is a proprietary compression format.

(8) Verifying ATPG Patterns

Ensure Static Timing Analysis was correctly performed before simulating any ATPG

patterns. Perform gate-level simulation in your sign-off environment.

二、高级命令解释

1. collapsed

set faults -report collapsed

The target coverage is affected by your use of the set fault -reportcommand. If fault

reporting is set to collapsed, the target percentage is in collapsed fault numbers. If

fault reporting is set to uncollapsed, the target percentage is in uncollapsed numbers.

The test coverage obtained through the uncollapsed fault list is usually higher and

within a few percentage points of the test coverage obtained through the collapsed

fault list (note, however, test coverage can slightly more with the fault report set to

collapsed compared to the test coverge with fault coverage set touncollapsed). To be

conservative, set fault reporting to collapsed before you generate patterns for a

specific target coverage. When you have finished, display the test coverage using the

uncollapsed fault list numbers. Often, the actual test coverage achieved will be higher

than your target.

2. ndetects

run atpg -ndetects 1

N-detection attempts to detect faults ntimes in ATPG. The default is one fault

detection. During fault simulation, the fault is kept in the active list until it is detected

ntimes. Studies have shown that detecting faults with multiple patterns helps catch

defects that cannot be modeled with standard fault models. Examples include

transistor stuck-open or cell-level n size, memory consumption, and

runtime will be larger than with the default one fault the exception of

the IDDQ and path delay fault models, all other fault models are supported.

Distributed processing, Full-Sequential ATPG, and fault simulation are not supported.

3. sensitive

set patterns external /*path/file_name.v –sensitive

TetraMAX automatically determines what type of netlist is referenced and reads the

file to collect design and module descriptions. By default, Verilog netlists are treated

as case-sensitive; EDIF and VHDL netlists are treated as case-insensitive. If you want

to override the default, add-sensitive or-insensitive at the end of the command.

al

set patterns external /*path/file_name.v –sensitive

If you have some vectors in the external buffer before starting distributed ATPG, they

will be automatically be transferred into the internal buffer. The new vectors created

during distributed ATPG will be added to this existing set of vectors. After the run is

complete, you will have both the external vectors and the ATPG created vectors in the

internal pattern buffer. If you do not want to merge those sets, you have to clean the

external buffer before starting distributed ATPG by issuing a “set pattern –delete”

command.

三、疑点解答

工具究竟是用来做什么的，其实现了什么功能，有什么实际意义？

TMAX是一款对已综合的门级电路进行故障仿真和分析的工具，可以分析和评估电路的可测性，并可给出故障列表、故障覆盖率、测试图形等结果。实际工程中，主要有两个用途：（1）评估和分析被测电路的可测性，从而为改进和优化电路可测性提供依据；（2）对已确定的被测电路，获得其对应的测试图形文件，如STIL文件。总的来讲，我们的目的就是为了获得与被测电路对应的故障覆盖率高且测试图形数目少的测试图形文件（当然，要想获得这样优质的图形文件，前提是被测电路要有良好的可测性，所以上述两个用途是相互依赖的）。而该文件正是后续将该电路流片后在ATE中测试时的测试矢量添加依据，换句话说，ATE测试该电路的实体时，所用的测试激励就是该图形文件。所以说，TMAX工具基于综合后的门级网表的前期模拟就是为后续实体电路在ATE上测试时提供高效的图形文件，之所以要高效，是因为ATE的测试成本非常昂贵，低效的测试图形一方面不能尽可能地检测电路故障，另一方面会花费较长的测试时间，从而提高了测试成本。

2.其操作方式有命令和按键两种，各自的优缺点是什么，两者具体有什么关系？

TMAX提供了命令和按键两种操作方式，两种方法均可实现相应的功能，是相通的，且可以相互联合使用。按键方式简单明了，但需要对图形化界面比较熟悉，需要一步步地去找按键所在位置，效率较低，适合初学者；命令方式快捷高效，只需要在命令栏输入命令即可执行对应的功能，但其需要对流程熟悉，需要熟练掌握相关命令，所以适合专业者。由于实际应用中常用的操作是流程化的，且同一类问题的操作也往往是一致的，所以对于命令操作方式，工具提供了用脚本的方法，即通过读入脚本文件即可执行所有流程的操作，这样，既高效且复用性高。此处脚本就是一个流程中所有的命令集，获得该脚本的方法除了常规的用符合工具规范的命令语言去手动编写外，TMAX还提供了自动获取的方式，其具体方法是：先用按键方式去正确地一步步完成整个流程中的所有操作，然后点击History按钮（位于图形界面的命令栏窗口上方），接着点击弹出的Save Contents As…按钮，然后在弹出的对话框中选定存储路径并指定文件名，这样，便获得了与流程中所有按钮操作对应的命令集即tcl脚本文件，以后同流程的操作可直接读入该文件即可。顺便指出，读脚本文件命令是：source

/*path/file_，且该命令是在图形化界面的命令栏输入的。

文档编号：ygyllpf20150401xjtu

文档类型：转载、原创

版权声明：本文档所有图例及英文部分绝大多数直接摘自ATPG with TetraMAX Student

Guide 2004版，文中所有内容仅供学习交流之用，严禁任何形式的商业目的。

最后修订日期：2015/04/01