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2024年4月16日发(作者:公众平台)
AD9361
RF and BB PLL Synthesizer
User Guide
AD9361 RF and BB PLL Synthesizer User Guide
GENERAL DESCRIPTION
The AD9361 transceiver contains two identical RFPLL synthesizers to generate the required LO signals. One is programmed for the RX
channel and the other for the TX channel. The transceiver also contains a BBPLL synthesizer to generate the required sampling and
internal operational clocks. The PLL synthesizers are all of fractional–N architecture with completely integrated VCOs and loop filters.
They require no external parts to cover the entire frequency range of the device. This configuration allows the use of any convenient
reference frequency for operation on any channel with any sample rate. For FDD operation, the frequency of TX and RX can be different
and both RFPLL synthesizers operate simultaneously. For TDD operation, the RFPLL synthesizers alternately turn on as appropriate for
RX and TX frames.
ADI Confidential
REVISION HISTORY
3/11—1.0 Distribution
4/11—1.1 Edit formatting add table. Applies to R1 version.
6/11—2.0 Update fixed writes for R2. Add Fast Lock info, Ext LO.
9/11—2.1 Include FDD and TDD tables for R2. Add BBPLL section. Examples updated.
10/11—2.2 Fixed typos.
11/11—2.3 Clarified BBPLL loop filter table value usage
1/12—2.4 Added how to generate TDD script with FDD calibrations to TDD MODE – Faster Lock Times section.
Rev 2.4.
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Tel: 781.329.4700
Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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