中英文文献翻译

EMC Design for High Speed PCB's

Excessive emission of electromagnetic waves associated with transmitting

switching signals and the susceptibility of circuits, within the high-speed digital

system are forcing PCB designers to develop new design techniques.

In recognition of this, the Spectrum Management Agency (SMA) has introduced

an electromagnetic compatibility (EMC) framework in Australia. The phase-in time

frame proposed by the SMA is divided into four stages over two years, beginning

January 1, 1996.

The Australian Electronics Development Centre (AEDC) regularly presents two

courses: Advanced Design for Surface Mount Technology (SMT) and EMC - Solving

the Problem in both Australia and New Zealand. These courses provide excellent

background knowledge for both EMC design and compliancy.

Although the majority of EMC compliance issues are associated with equipment

chassis shielding/grounding and cabling, PCB engineers and designers must pay

attention to transmission line effects in high speed designs.

For example, the inherent timing requirements of a design will dictate the use of

different device families. Wherever possible, these logic families should be confined

geographically. Multiple pin grounds or controlled impedance connectors may mean

less routing real estate or higher component costs, but may also be the differentiating

factor between a functional and non-functional product. The transmission line

geometry and multilayer stack-up construction are critical factors. Impedance

matching, clock skewing, crosstalk, parallelism and power distribution all affect

signal integrity. And, though, there are EDA tools on the market that can help control

these problems, it's best to be familiar with the cause and effects of electromagnetic

interference and compatibility and how to maintain control of a design.

Radiation and Antenna

At high frequencies, traces on a PCB act as a mono-pole or loop antennas.

Differential-mode radiation is the electromagnetic radiation caused by currents

consisting of harmonic frequency components flowing in a loop in the PCB. The

radiation is proportional to the current loop area and the square of the frequency of the

signal. Common-mode radiation is the electromagnetic radiation caused by current

flowing in an unterminated trace (or terminated with a high input impedance device)

and may require load terminating resistors to eliminate reflections. The radiation

resembles that of a mono-pole antenna and the magnitude is proportional to the

current per line length and frequency.

Unfortunately, the high frequency components of the fundamental (lowest

frequency in a complex wave) radiate more readily because their shorter wavelengths

are comparable to trace lengths, which act as antennas. Consequently, although the

amplitude of the harmonic frequency components decreases as the frequency

increases, the radiated frequency varies depending on the antennas/traces

characteristics. For example, interference signals produced by computing devices tend

to lie in the 10 to 300 MHz region.

At what speed should there be concern about wave propagation rather than just

current in conductors? The rule is that transmission line effects become an important

design consideration when the trace length approaches 1/7 of the wave-length of the

signal being transported. If the system clock frequency is 300 MHz, the wavelength in

FR4 is about 0.5 m.

Clock Speed or Rise/Fall Time?

Generally, the system clock is a repetition rate of a square wave pulse, and the

pulse information of "1" or "0" is carried on the leading edge of the pulse. This edge

must be permitted to rise or fall as quickly as possible. Frequency and the rise time of

the signal are related by the relation:

Tr (rise time in nS) = 0.35 / frequency in GHz

Table 1 shows the rise times and wavelengths for common high-speed IC's.

This translates to a wavelength of about 375 mm in free air or 175 mm in FR4 and

100 mm in ceramic. Therefore, if the trace length is more than 25 mm for PCB's

fabricated from FR4, then the electromagnetic properties of the ECL signal and the

transmission line effects should be considered.

Therefore, the signal rise/fall time, instead of the signal clock frequency,

determines the critical signal speed. A steep rise/fall time may be slowed by loading

the signal line with a damping/backmatching resistor close to the source.

Characteristic Impedance

Fifty to eighty ohm characteristic impedance is often used in high-speed designs.

Lower impedance values cause excessive dI/dt crosstalk and can double the power

consumed to create a heat dissipation problem. Higher impedances not only produce

high crosstalk, but also produce circuits with greater EMI sensitivity and emission.

Table 2 illustrates the effect that physical properties have on the impedance (Zo)

of a transmission line.

The fields emanating from the surface of a conventional single/double-sided board

are not guided by a controlled return conductor (i.e. reference plane). Rather,the fields

tend to terminate on adjacent traces, which creates crosstalk. Some of these fields

escape the surface of the PCB totally and radiate outward.

However, multilayer PCB's have ground and power distribution conductors

embedded as planes in the substrate. The return currents for the signal traces flow

through the reference plane, which is in close proximity to the trace. Also, the use of

planes provides the low impedance power distribution necessary for good supply

decoupling.

Enclosing signal traces between the ground and power planes provides a shield

which reduces both radiation (by up to 45 dB) and susceptibility to radiation, as well

as providing ESD protection. It is good practice to route high speed, fast rise time

signals between these planes to eliminate radiation. If a large capacitance exists

between the rails, both ground and power planes may be used as reference planes.

Recent studies, conducted by Hewlett Packard have found that there is up to 20

dB greater emissions from edge-located traces compared to traces located in the

centre of the board on outer layers. Yet, the same test performed on buried traces

indicated no change as the traces were placed nearer the PCB edges.

Recently, software has become available that can be used to calculate the

impedance and the velocity of propagation of each layer for a given trace width. For

reduced crosstalk, alternate layers should be rotated by 90 degrees (e.g. layer one =

horizontal, layer three = vertical, layer four = horizontal, etc).

Generating Noise

Clock circuits have the highest toggle rates of all circuits and are the primary

source of noise generated in digital circuits. Clock timing and skew are critical factors

affecting circuit performance. It is best to centrally locate the clock generator and

distribute it radially. Radiated fields from the outward flowing currents tend to cancel,

which reduces and synchronises propagation delays throughout the board. Equal

mark-to-space ratios with controlled rise/fall times also help reduce noise by

removing even harmonics.

In high-speed systems, the clock cycle time is usually shorter than the propagation

delay for a signal to travel from one device to another. For the system to perform

correctly at high speeds, a well-controlled propagation time is required, and

adjustments in the timing skew for some signals may be necessary. Tuned delay can

be achieved with the aid of software. Alternatively, trace lengths can be equalised

manually to avoid skew by using a star routing pattern from the source.

Component Density = Trace Density = Crosstalk

Generally, an assembly is populated as densely as possible with SMDs to

minimise the size of the board and reduce propagation time. The result is, of course,

that traces must run close to each other, which creates crosstalk. Crosstalk is the

transfer of pulse energy by the electromagnetic field from a source line to a victim

line. The intensity of the coupled signal decreases with shorter adjacent line segments,

wider line separations, lower line impedance and longer pulse rise times.

Field solver software is recommended to predict transmission line characteristic

impedances, propagation velocities and crosstalk. As clock speeds increase, this may

become mandatory. To accurately estimate delays and crosstalk, a layer stackup must

be coupled with the field solver. The result is a quick and accurate characterisation of

the layout traces that is dynamically updated on the fly. Note that the dielectric

constant of FR4 material can vary by as much as 20%.

Logic Families Don't Mix

Mixing logic families is not advised because of their differences in voltage swings,

noise margins and logic levels. For example, Schottky TTL swings 3 V while the ECL

family has only 100 mV DC noise margin. Mixing these two logic families could

cause significant undesired coupling.

For high-speed devices, switching activity is accompanied by equally high-speed

demands for changes in current from the power supply. If several devices are

switching at the same instant, the power distribution system must be able to supply

the current while maintaining the supply voltage within the specified limits. Low

inductance supply connections to the devices (one of the many advantages of SMDs)

and high capacitance distributed across the board reduces the problem.

Decoupling

Decoupling capacitors provide current to devices until a power supply can

respond. High frequency switching, composing a broad spectrum of current

frequencies, requires several low to high frequency capacitors. This requirement is

because a single capacitor typically cannot provide such a broad frequency.

A chip capacitor should be located as close as possible to a device's supply pins.

To reduce series inductance the capacitor lands should be connected to the power pins

using a trace width of at least 20 mil. To prevent common-mode noise, keep the trace

as short as possible and do not connect directly to the plane via a thermal relief.

Tantalum capacitors (e.g. 10 uF) should be spaced evenly across the board,

generally, one for every six or so ICs. These tantalum's provide current for the low

frequency component of the switching transient.

Mixed Signals and Split Planes

When both analogue and digital devices are used on the same PCB, partitioning

the ground plane is usually necessary. The components should be positioned so that

all the devices are grouped in such a way that no digital signals will cross over the

analog ground and no analog signals will cross over the digital ground.

Split or isolated planes can be used to effectively force the current associated with

a particular circuit into a specific area that can be decoupled or grounded. The split

plane confines high frequency currents and return paths so they can not flow across or

through adjacent low frequency circuits, preventing crosstalk.

Shielding and Large Components

Large PQFP's typically require installation in a shielded equipment enclosure for

compliance. However, the same piece of silicon housed in a PGA or BGA package

may achieve compliance. The PGA and BGA packages have an efficient heatsink on

the top of the package, which not only serves to dissipate the heat, but also acts as an

EMI shield.

Routing

Orthogonal trace corners should be avoided. The debate rages, but as frequencies

and edge rates continue to rise, ninety degree corners introduce excess capacitance

and cause a small change in characteristic impedance. This becomes disastrous at high

frequencies (e.g. 100 MHz) when electrons virtually fly off the sharp corners of the

bend. Forty-five degree turns, with a minimum segment length of twice the trace

width, are better. Arced corners, with the inside radius of at least the trace width, are

by far the best approach for high-speed signals.

Conclusion

The competitive necessity to take maximum advantage of circuit speed and

density has forced designers to pay more attention to the problems associated with

transmission line effects on PCB's. In order to accurately predict potential problem

areas, minimise electromagnetic interference and susceptibility and verify their design,

today's PCB designers not only need to plan for EMC but also must use software to

analyse the physical layout. As clock speeds approach 50 MHz, signal integrity issues

should be considered.

高速PCB板的EMC设计

过强的电磁辐射会使开关信号的传输受到影响，也会干扰电流。于是，高速

数字系统迫使PCB设计者去探索新的设计技术。

认识到这一点之后，电磁管理机构在澳大利亚初次建立了电磁兼容体系。电

磁管理机构将这一分阶段引入的框架体系在两年内分四个阶段进行。初始阶段的

开始时间是1996年1月1日。

澳大利亚电子发展中心有计划的推出了两个进程：推进表面峰值设计和电磁

兼容性设计。这两大进程同时在澳大利亚和新西兰展开。这些进程为电磁兼容性

设计和规范提供了一个良好的学术背景。

虽然许多电磁兼容性标准跟设备的框架（外壳）、屏蔽、接地、绝缘有关，

但是PCB工程师和设计者们更必须把注意力放在传输线对高速信号传输的影响

上。

例如，不同用途的设计体系要求要有如之相匹配的固有域值要求。无论在什

么情况下，逻辑体系都将受到具体使用场合的限制，多点接地或通过阻抗接地都

会意味着降低线路等级或增加阻抗损耗。但对于功能产品和非功能产品有不同的

临界系数，传输线的几何形状和多层设计会存在一个临界系数，导线阻抗、时钟

信号斜率、串扰、线路平行、功率分配都会影响信号的完整性。市场上有很多

EDA工具能够帮助控制这些问题，但对于一个具体的体系如果能够弄清电磁辐

射和谐波产生的原因和影响就能够保证信号传输的完整性。

辐射和天线

在高频情况下，PCB板的线路扮演了一个单极天线或环状天线的角色。不同

类型辐射的实质都相同——电磁波。这些电磁波是由流过PCB环路形成的谐波

组成。辐射强度与电流环路面积以及信号频率成正比。普通类型的辐射也是一种

电磁波，该电磁波也是由电流流经无终止的线路（或为高阻抗设计）形成的这种

辐射就好像一根单极性的天线，辐射大小跟线路长度和信号频率成正比。

不幸的是，基波（复合波中频率最低的波）的高频成分更容易产生辐射，因

为它的波长跟传输线路的尺寸相比要小的多，这样传输线路就好象一根单极天

线，虽然谐波的幅值会随着频率的降低而增大，但电磁波的频率是由天线/线路

的性质决定的。例如，界面信号频率的计算机仿真频率在10到300兆赫兹之间。

哪种速度的设计应该考虑到波的传输是否仅与导体中的电流有关呢？规则

是这样的：当线路长度接近信号波长的1/7时，就必须考虑线路的重要性。如果

系统信号频率为300M，则FR4板的波长大概为0.5米,陶瓷中约为100mm。

时钟速度或上升/下降时间

总的说来，系统时钟是一个比率重复的方波脉冲，这个脉冲所表示的信息为

“1”或“0”，脉冲边缘的陡度应尽可能的大，信号上升沿时间与信号频率的关

系为：

Tr=0.35/f

其中Tr的单位为ns，f的单位为GHz。

从这个函数关系式可以知道，电磁波在空气中的波长约为375mm,在FR4板

中的波长为175mm。所以，假如FR4板中的线路长度大于25mm，那么就必须

考虑线路设计对信号电磁特性的影响。

因此，信号的上升和下降沿时间、信号时钟频率都将影响信号的临界速度，

对于线路逐渐变窄或导线阻抗接近信号源阻抗的，就应该降低所加载的时钟信号

的上升/下降沿的陡度。

阻抗特性

50到80欧姆的电阻经常被用在高速设计中，低阻值电阻容易导致过大的

di/dt串扰以及能量损耗和高发热量问题。大电阻不仅会产生大的串扰，同时也会

产生对电磁敏感的电流和辐射。

来自单面或双面板的辐射不会被参考平面所传导，更确切的说，线路会对靠

近它的区域造成串扰。有鞋敏感的区域应设置隔离或设法让串扰向外辐射。

但是，多数PCB板都有接地和功率分配，这样线路就有可能被埋如离层，

在走线附近设置参考平面，让信号电流流经这一平面，这个有用的平面提供了一

个低阻抗的功率分配和必要的退耦处理。

处于地线和电源线之间的信号线应该设置屏蔽装置，以此来减少辐射（大于

45dB）和降低受干扰的几率，例如像ESD保护，它有利于对高速线路的保护、

消除辐射对高速上升沿时钟信号的干扰。如果在平行面之间存在大的分布电容，

那么地和电源平面都可以用做参考平面。

Hewlett Packard 的最新研究发现，在外层板的中心会产生一个高达20dB的

辐射，而同样的测试表明埋入的线路和处于边沿的线路所受到的辐射是一样的。

今年来，可以利用软件计算给定线宽线路层与层之间的阻抗和电压值，为了

减少串扰，相邻面的走线应形成90度角。（例如，第一层为水平、第三层为垂直、

第四层为水平）

噪声的形成

在所有的电流中，时钟信号的电流有最高的重复速率，而噪声源就是由数字

电流产生。时钟周期和斜率是影响电流工作性能的主要因素。中心位置是时钟信

号产生和分配辐射的最佳位置。夹杂在电流中的外来干扰会被抵消掉，其通过板

的时候会被削弱，同时传输时间也会滞后。另外，较陡的上升下降沿时间也有利

用减少噪声。

在高速系统中时钟周期通常比信号从一个设备传到另一设备所需的时间要

短，要让一个系统在高频情况下有一个较好的抗干扰特性，一个好的控制时间是

必需的，对某些信号时钟斜率的调节作用也是必要的。延时的调节可以用软件来

实现。

组成密度=线路密度=串扰

总的来说，元器件的安装应尽可能的密集，采用贴片封装形式的元件有利于

减小电路板的面积和降低传播时间。要做到这一点，走线就必须彼此相互靠近，

这样做的结果是会产生串扰，串扰就是脉冲能量以电磁波的形式从源线路传到受

干扰线路。线路的临近部分、宽线分离处、低阻抗线路以及长的脉冲上升沿时间

都会使双极性信号的强度受到削弱。

Field Solver软件被推荐用于线路特性阻抗、传导电压和串扰预测，如果线路

时钟速度提高的话，那么这一步将变的必不可少的。要精确估算时延和串扰，多

层板的层数必须设计成偶数。应该注意到，FR4板材的绝缘稳定性会有多达20%

的波动。

逻辑电平不能混合

将逻辑电平混合是不允许的，因为他们的震荡电压、噪声差数和逻辑水平不

同。例如，TTL电平电压波动有3V，而ECL只有100Mv的直流噪声差数。如

果将这两种逻辑电平混合就会导致严重的偶合问题。

对于高速设备，开关的高速动作过程会引起大的电流变化，如果多台设备的

开关同时动作，那么只有在电源电压保持不边或电源无功率极限的前提下才能做

到功率的正常分配。降低设备引线长度（贴片元件的优点之一）、提高板的分布

电容都有利于减少这些问题。

退耦

退耦电容的作用是在电源无应答的情况下为设备提供电流，高频开关动作会

产生宽频带的电流，故必须为之配备从小到大的退耦电容以此来吸收不同频率的

骚扰，因为一个固定容量的电容不可能提供一个很宽的偶合频率。

电容的安装应该尽可能的靠近设备的电源入口，为了减小导线的分布电容，

电容与电源线的连接线路的宽应大于20mil，为了抑制共模干扰，应尽可能缩短

引线长度以及尽量避免引线经过或靠近散热板。

钽电容（如10μF）应匀称的分布安装，这种电容为开关动作所产生的低频

成分提供瞬时电流。

信号的混合和分离

当数字设备和模拟设备同时做在一快PCB板上时，划分板的区域是必要的，

即将模拟部分和数字部分分离开来，这样模拟和数字部分就可以各行其道，数字

信号和模拟信号也不会相互干扰，即不会有模拟信号通过数字部分也不会有数字

信号通过模拟部分。

分离和分割用于影响电流的汇合，尤其是电流流经那些无偶合和有接地的区

域。区域分离限制了高频电流和回路，这样高频电流就不会通过或临近低频电流，

以此来避免串扰的产生。

屏蔽和大型零部件

大型的塑料方块扁平封装元件的安装需要圈出特别的区域。同样一片硅块用

GPA或BPA封装也可以实现。GPA或BPA封装的芯片的背面具有更高的散热性

能，它的被面不仅仅用做散热之用还具有抗干扰的作用，即有EMI屏蔽作用。

线路

应当避免线路以90度教拐弯。对于这一问题的讨论很是激烈，但是像对频

率和时钟上升沿的讨论激烈程度还在上升，90度角的转弯回引入过大的分布点

燃和导致一个小的阻抗特性变化。这将在高频条件下当电流流经角度尖端时产生

严重的后果。45度的转角使两条线路之间具有最小的走线。以线路宽度为半径

弧线转弯是最有利于高速信号的传输。

结束语

最优的电流速度和密度竞争迫使设计者把更多的精力投入到PCB线路设计

对信号传输的影响上。为了更精确地预知线路区域所存在的潜在问题、尽可能地

减小干扰、减少受干扰的机率以及检验他们的设计，今天的PCB板设计者们不

仅仅需要注意EMC设计同时也要求他们能利用软件去分析板的分布物理特性。

当时钟频率接近50MHz时信号的完整性问题就应当予以重视。