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错误答案：

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );
	
    wire [99:0] co;
    genvar i;    
    generate
        for(i=0;i<=99;i=i+1) begin: looper
            if(i==0)
                    bcd_fadd add0(a[3:0],b[3:0],cin,co[0],sum[3:0]);
            else
                bcd_fadd add0(a[4i+3:4i)],b[4i+3:4i],co[i-1],co[i],sum[4i+3:4i]);
        end
    endgenerate
    
    assign cout = co[99];
    
endmodule

Error (10170): Verilog HDL syntax error at top_module.v(14) near text: "i";  expecting "]". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/h/work/hdlbits.6672762/top_module.v Line: 14

正确答案：

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );
	
    wire [99:0] co;
    genvar i;    
    generate
        for(i=0;i<=399;i=i+4) begin: looper
            if(i==0)
                    bcd_fadd add0(a[3:0],b[3:0],cin,co[0],sum[3:0]);
            else
                    bcd_fadd add0(a[i+3:i],b[i+3:i],co[(i>>2)-1],co[i>>2],sum[i+3:i]);
        end
    endgenerate
    
    assign cout = co[99];
    
endmodule

本文标签： 错题集 HDLBits

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