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2024年12月27日发(作者：sw球员版是什么意思)
Thermal Management Strategy
As described in this section, Xilinx relies on a multi-pronged approach with regards to the
heat-dissipating potential of 7series devices.
Cavity-Up Plastic BGA Packages
BGA is a plastic package technology that utilizes area array solder balls at the bottom of the
package to make electrical contact with the circuit board in the users system. The area array
format of solder balls reduces package size considerably when compared to leaded
products. It also results in improved electrical performance as well as having higher
manufacturing yields. The substrate is made of a multi-layer BT (bismaleimide triazene)
epoxy-based material. Power and GND pins are grouped together and signal pins are
assigned to the perimeter for ease of routing on the board. The package is offered in a
die-up format and contains a wire-bond device covered with a mold compound. As shown
in the cross section of Figure5-2, the BGA package contains a wire-bond die on a
single-core printed circuit board with an overmold.
Plastic MoldPlated Copper Conductor
SoldermaskBT (PCB Laminate)Solder Ball
UG475_c5_01_042012
Figure 5-2:Cavity-Up Ball Grid Array Package
The key features/advantages of cavity-up BGA packages are:
•
•
•
Low profile and small footprint
Enhanced thermal performance
Excellent board-level reliability
Wire-Bond Packages
Wire-bond packages meet the demands required by miniaturization while offering
improved performance. Applications for wire-bond packages are targeted to portable and
consumer products where board space is of utmost importance, miniaturization is a key
requirement, and power consumption/dissipation must be low. By employing 7series FPGA
wire-bond packages, system designers can dramatically reduce board area requirements.
Xilinx wire-bond packages are rigid BT-based substrates (see Figure5-3).
7 Series FPGAs Packaging
UG475 (v1.18) July 16, 2019
Chapter 3:Device Diagrams
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
34
AH
AJ
AK
1
234567897282930
17
17
18
18
17
18
18
17
18
18
17
15
15
15
14
14
15
15
15
17
16
16
17
16
16
16
16
16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
14
0
3312
32
32
33
3312
32
32
3312
32
32
3312
13
13
12
13
12
13
13
14
V
W
Y
AA
AB
AC
13
AD
AE
AF
AG
AH
AJ
AK
0
14
0
0
14
33
0
34
34
34
34
34
34
234567897282930
Power Pins
#VCCO_#
VCCINT
VCCAUX
#VCCAUX_IO_G#
VCCBRAM
VCCBATT_0
VCCADC_0
GNDADC_0
#
#
#
MGTVCCAUX
MGTVCCAUX_G# or MGTHVCCAUX_G#
MGTAVCC
MGTAVCC_G# or MGTHAVCC_G#
MGTAVTT
MGTAVTT_G# or MGTHAVTT_G#
GND
ug475_c3_28_052311
Figure 3-112:FB900, FBG900, and FBV900 Packages—XC7K325T and XC7K410T
Power and GND Placement
7 Series FPGAs Packaging
UG475 (v1.18) July 16, 2019
Chapter 3:Device Diagrams
FF676, FFG676, FFV676, and RF676 Packages—XC7K160T,
XA7K160T, XC7K325T, and XC7K410T
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
1
234567891617181926
A
V
V
V
E
EC
B
B
BB
B
C
B
U
D
E
F
V
V
EYB
G
H
EDss
sr
r
sB
B
s
s
J
K
L
M
N
P
R
T
ssU
V
W
s
Y
AA
AB
AC
AD
AE
AF
V
V
V
2
E
G
V
K
MS
S
S
S
J
s
P
IOL
10
234567891617181926
User I/O Pins
IO_LXXY_#
sIO_XX_#
Transceiver Pins
E
V
V
MGTAVCC_G#
MGTAVTT_G#
MGTVCCAUX_G#
MGTAVTTRCAL
MGTRREF
MGTREFCLK1/0P
MGTREFCLK1/0N
MGTXRXP
MGTXRXN
MGTXTXP
MGTXTXN
E
V
MGTHAVCC_G#
MGTHAVTT_G#
MGTHRXP
MGTHRXN
MGTHTXP
MGTHTXN
Y
0
1
2
P
K
I
O
M
D
J
L
C
Dedicated Pins
CCLK_0
CFGBVS_0
DONE_0
DXP_0
DXN_0
GNDADC_0
INIT_B_0
M0_0
M1_0
M2_0
PROGRAM_B_0
TCK_0
TDI_0
TDO_0
TMS_0
VCCADC_0
VCCBATT_0
n
S
S
S
S
VP_0
VN_0
VREFP_0
VREFN_0
Other Pins
GND
VCCAUX_IO_G#
VCCAUX
VCCINT
VCCO_#
VCCBRAM
NC
Multi−Function Pins
B
B
B
B
B
B
B
B
U
r
ADV_B
FCS_B
FOE_B
MOSI
FWE_B
DOUT_CSO_B
CSI_B
PUDC_B
RDWR_B
RS0−RS1
AD0P/AD0N−AD15P/AD15N
EMCCLK
VRN
VRP
VREF
D00−D31
A00−A28
DQS
MRCC
SRCC
V
G
ug475_c3_29_090511
Figure 3-113:FF676, FFG676, FFV676, and RF676 Packages—XC7K160T, XA7K160T, XC7K325T, and
XC7K410T Pinout Diagram
7 Series FPGAs Packaging
UG475 (v1.18) July 16, 2019
Chapter 3:Device Diagrams
7 Series FPGAs Packaging
UG475 (v1.18) July 16, 2019
Chapter 3:Device Diagrams
FF901, FFG901, and FFV901 Packages—XC7K355T
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
1
234567897282930
nn
n
nn
n
n
n
n
nn
n
n
n
n
n
s
s
B
s
B
s
nn
n
n
n
s
A
B
C
D
E
F
G
H
J
K
L
M
N
r
U
B
B
s
s
B
P
R
T
U
BB
V
W
Y
AA
n
n
n
n
n
n
n
n
nn
n
nn
n
n
nn
n
n
nn
n
n
ns
AB
AC
AD
AE
AF
AG
AH
AJ
AK
V
VV
V
V
E
EV
En
n
En
n
V
VE
Y
E
V
VE
V
I
M
KC
O
n
n
n
n
n
E
V
VE
GB
r
S
S
S
S
J
V
E
V
VE
V
L
s
n
V
n
P2
10
n
n
n
n
nn
n
n
n
n
nE
n
nE
n
nn
n
n
n
n
n
n
n
n
n
n
n
n
ns
s
s
E
V
VEnnD
E
V
VE
nn
nn
nnn
n
E
nV
n
V
V
23456
n
V
7
nV
n
897282930
User I/O Pins
IO_LXXY_#
sIO_XX_#
Transceiver Pins
E
V
V
MGTAVCC_G#
MGTAVTT_G#
MGTVCCAUX_G#
MGTAVTTRCAL
MGTRREF
MGTREFCLK1/0P
MGTREFCLK1/0N
MGTXRXP
MGTXRXN
MGTXTXP
MGTXTXN
E
V
MGTHAVCC_G#
MGTHAVTT_G#
MGTHRXP
MGTHRXN
MGTHTXP
MGTHTXN
Y
0
1
2
P
K
I
O
M
D
J
L
C
Dedicated Pins
CCLK_0
CFGBVS_0
DONE_0
DXP_0
DXN_0
GNDADC_0
INIT_B_0
M0_0
M1_0
M2_0
PROGRAM_B_0
TCK_0
TDI_0
TDO_0
TMS_0
VCCADC_0
VCCBATT_0
n
S
S
S
S
VP_0
VN_0
VREFP_0
VREFN_0
Other Pins
GND
VCCAUX_IO_G#
VCCAUX
VCCINT
VCCO_#
VCCBRAM
NC
Multi−Function Pins
B
B
B
B
B
B
B
B
U
r
ADV_B
FCS_B
FOE_B
MOSI
FWE_B
DOUT_CSO_B
CSI_B
PUDC_B
RDWR_B
RS0−RS1
AD0P/AD0N−AD15P/AD15N
EMCCLK
VRN
VRP
VREF
D00−D31
A00−A28
DQS
MRCC
SRCC
V
G
ug475_c3_37_090511
Figure 3-121:FF901, FFG901, and FFV901 Packages—XC7K355T Pinout Diagram
7 Series FPGAs Packaging
UG475 (v1.18) July 16, 2019
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