FPGA可编程逻辑器件芯片XCVU13P-L2FLGA2577E中文规格书

DS890 (v3.13) July 21, 2020Product Specification

General Description

Xilinx® UltraScale™ architecture comprises high-performance FPGA, MPSoC, and RFSoC families that address a vast spectrum of

system requirements with a focus on lowering total power consumption through numerous innovative technological

advancements.

Kintex® UltraScale FPGAs: High-performance FPGAs with a focus on price/performance, using both monolithic and

next-generation stacked silicon interconnect (SSI) technology. High DSP and blockRAM-to-logic ratios and next-generation

transceivers, combined with low-cost packaging, enable an optimum blend of capability and cost.

Kintex UltraScale+™ FPGAs: Increased performance and on-chip UltraRAM memory to reduce BOM cost. The ideal mix of

high-performance peripherals and cost-effective system implementation. Kintex UltraScale+ FPGAs have numerous power

options that deliver the optimal balance between the required system performance and the smallest power envelope.

Virtex® UltraScale FPGAs: High-capacity, high-performance FPGAs enabled using both monolithic and next-generation SSI

technology. Virtex UltraScale devices achieve the highest system capacity, bandwidth, and performance to address key market and

application requirements through integration of various system-level functions.

Virtex UltraScale+ FPGAs: The highest transceiver bandwidth, highest DSP count, and highest on-chip and in-package memory

available in the UltraScale architecture. Virtex UltraScale+ FPGAs also provide numerous power options that deliver the optimal

balance between the required system performance and the smallest power envelope.

Zynq® UltraScale+ MPSoCs: Combine the Arm® v8-based Cortex®-A53 high-performance energy-efficient 64-bit application

processor with the Arm Cortex-R5F real-time processor and the UltraScale architecture to create the industry's first

programmable MPSoCs. Provide unprecedented power savings, heterogeneous processing, and programmable acceleration.

Zynq® UltraScale+ RFSoCs: Combine RF data converter subsystem and forward error correction with industry-leading

programmable logic and heterogeneous processing capability. Integrated RF-ADCs, RF-DACs, and soft-decision FECs (SD-FEC)

provide the key subsystems for multiband, multi-mode cellular radios and cable infrastructure.

Family Comparisons

Table 1:Device Resources

Kintex

UltraScale

FPGA

MPSoC Processing System

RF-ADC/DAC

SD-FEC

System Logic Cells (K)

Block Memory (Mb)

UltraRAM (Mb)

HBM DRAM (GB)

DSP (Slices)

DSP Performance (GMAC/s)

Transceivers

Max. Transceiver Speed (Gb/s)

Max. Serial Bandwidth (full duplex) (Gb/s)

Memory Interface Performance (Mb/s)

I/O Pins

768–5,520

8,180

12–64

16.3

2,086

2,400

312–832

1,368–3,528

6,287

16–76

32.75

3,268

2,666

280–668

600–2,880

4,268

36–120

30.5

5,616

2,400

338–1,456

318–1,451

12.7–75.9

356–1,843

12.7–60.8

0–81

783–5,541

44.3–132.9

862–8,938

23.6–94.5

90–360

0–16

1,320–12,288

21,897

32–128

58.0

8,384

2,666

208–2,072

240–3,528

6,287

0–72

32.75

3,268

2,666

82–668

3,145–4,272

7,613

8–16

32.75

1,048

2,666

280–408

103–1,143

4.5–34.6

0–36

Kintex

UltraScale+

FPGA

Virtex

UltraScale

FPGA

Virtex

UltraScale+

FPGA

Zynq

UltraScale+

MPSoC

✓

Zynq

UltraScale+

RFSoC

✓

✓

✓

678–930

27.8–38.0

13.5–22.5

DS890 (v3.13) July 21, 2020

Product Specification

UltraScale Architecture and Product Data Sheet: Overview

RF Data Converter Subsystem

ZynqUltraScale+ RFSoCs contain an RF data converter subsystem consisting of multiple RF-ADCs and

RF-DACs.

RF-ADCs

The RF-ADCs can be configured individually for real input signals. RF-ADCs in all devices other than the

XCZU43DR can also be configured as a pair for I/Q input signals. The RF-ADC tile has one PLL and a

clocking instance. Decimation filters in the RF-ADCs can operate in varying decimation modes at 80% of

Nyquist bandwidth with 89dB stop-band attenuation. Each RF-ADC contains a 48-bit numerically

controlled oscillator (NCO) and a dedicated high-speed, high-performance, differential input buffer with

on-chip calibrated 100 termination.

RF-DACs

The RF-DACs can be configured individually for real outputs. RF-DACs in all devices other than the

XCZU43DR can also be configured as a pair for I/Q output signal generation. The RF-DAC tile has one PLL

and a clocking instance. Interpolation filters in the RF-DACs can operate in varying interpolation modes at

80% of Nyquist bandwidth with 89dB stop-band attenuation. Each RF-DAC contains a 48-bit NCO.

Soft-Decision Forward Error Correction (SD-FEC)

Some members of the ZynqUltraScale+ RFSoC family contain integrated SD-FEC blocks capable of

encoding and decoding using LDPC codes and decoding using Turbo codes.

LDPC Decoding/Encoding

A range of quasi-cyclic codes can be configured over an AXI4-Lite interface. Code parameter memory can

be shared across up to 128 codes. Codes can be selected on a block-by-block basis with the encoder able

to reuse suitable decoder codes. The SD-FEC uses a normalized min-sum decoding algorithm with a

normalization factor programmable from 0.0625 to 1 in increments of 0.0625. There can be between 1 and

63 iterations for each codeword. Early termination is specified for each codeword to be none, one, or both

of the following:





Parity check passes

No change in hard information or parity bits since last operation

Soft or hard outputs are specified for each codeword to include information and optional parity with 6-bit

soft log-likelihood ratio (LLR) on inputs and 8-bit LLR on outputs.

DS890 (v3.13) July 21, 2020

Product Specification

UltraScale Architecture and Product Data Sheet: Overview

DS890 (v3.13) July 21, 2020

Product Specification

UltraScale Architecture and Product Data Sheet: Overview

Clock Distribution

Clocks are distributed throughout UltraScale devices via buffers that drive a number of vertical and

horizontal tracks. There are 24 horizontal clock routes per clock region and 24 vertical clock routes per

clock region with 24 additional vertical clock routes adjacent to the MMCM and PLL. Within a clock region,

clock signals are routed to the device logic (CLBs, etc.) via 16 gateable leaf clocks.

Several types of clock buffers are available. The BUFGCE and BUFCE_LEAF buffers provide clock gating at

the global and leaf levels, respectively. BUFGCTRL provides glitchless clock muxing and gating capability.

BUFGCE_DIV has clock gating capability and can divide a clock by 1 to 8. BUFG_GT performs clock division

from 1 to 8 for the transceiver clocks. In MPSoCs and RFSoCs, clocks can be transferred from the PS to the

PL using dedicated buffers.

Memory Interfaces

Memory interface data rates continue to increase, driving the need for dedicated circuitry that enables

high performance, reliable interfacing to current and next-generation memory technologies. Every

UltraScale device includes dedicated physical interfaces (PHY) blocks located between the CMT and I/O

columns that support implementation of high-performance PHY blocks to external memories such as

DDR4, DDR3, QDRII+, and RLDRAM3. The PHY blocks in each I/O bank generate the address/control and

data bus signaling protocols as well as the precision clock/data alignment required to reliably

communicate with a variety of high-performance memory standards. Multiple I/O banks can be used to

create wider memory interfaces.

As well as external parallel memory interfaces, UltraScale architecture-based devices can communicate to

external serial memories, such as Hybrid Memory Cube (HMC), via the high-speed serial transceivers. All

transceivers in the UltraScale architecture support the HMC protocol, up to 15Gb/s line rates. UltraScale

devices support the highest bandwidth HMC configuration of 64lanes with a single FPGA.

Block RAM

Every UltraScale architecture-based device contains a number of 36Kb block RAMs, each with two

completely independent ports that share only the stored data. Each block RAM can be configured as one

36Kb RAM or two independent 18Kb RAMs. Each memory access, read or write, is controlled by the clock.

Connections in every block RAM column enable signals to be cascaded between vertically adjacent block

RAMs, providing an easy method to create large, fast memory arrays, and FIFOs with greatly reduced

power consumption.

All inputs, data, address, clock enables, and write enables are registered. The input address is always

clocked (unless address latching is turned off), retaining data until the next operation. An optional output

data pipeline register allows higher clock rates at the cost of an extra cycle of latency. During a write

operation, the data output can reflect either the previously stored data or the newly written data, or it can

remain unchanged. Block RAM sites that remain unused in the user design are automatically powered

DS890 (v3.13) July 21, 2020

Product Specification

UltraScale Architecture and Product Data Sheet: Overview

Packaging

The UltraScale devices are available in a variety of organic flip-chip and lidless flip-chip packages

supporting different quantities of I/Os and transceivers. Maximum supported performance can depend on

the style of package and its material. Always refer to the specific device data sheet for performance

specifications by package type.

In flip-chip packages, the silicon device is attached to the package substrate using a high-performance

flip-chip process. Decoupling capacitors are mounted on the package substrate to optimize signal

integrity under simultaneous switching of outputs (SSO) conditions.

DS890 (v3.13) July 21, 2020

Product Specification