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2024年3月25日发(作者：c语言培训班哪个平台好)

专利内容由知识产权出版社提供

专利名称：Built-in self test (BIST) technology for

testing field programmable gate arrays

(FPGAs) using partial reconfiguration

发明人：Tassanee Payakapan,Lee Ni Chung,Shahin

Toutounchi

申请号：US11284455

申请日：20051121

公开号：US07302625B1

公开日：20071127

专利附图：

摘要：A Built-in Self Test (BIST) system is provided in a Field Programmable Gate

Array (FPGA) that can adjust test signal patterns provided for testing after partial

reconfiguration of the FPGA. The BIST system includes a decoder that monitors I/O

signals and provides an output indicating when I/O signals change indicating partial

reconfiguration has occurred. The decoder output is provided to a BIST test signal

generator providing signals to an IP core of the FPGA as well as a BIST comparator for

monitoring test results to change test signals depending on the partial configuration

mode.

申请人：Tassanee Payakapan,Lee Ni Chung,Shahin Toutounchi

地址：San Jose CA US,San Jose CA US,Pleasanton CA US

国籍：US,US,US

代理人：Thomas A. Ward,Kevin T. Cuenot

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